1. Field of the Invention
The present invention relates generally to a method for fabricating a chip carrier, such as a printed circuit board, and more particularly to a method for fabricating a chip carrier which includes at least one photo-via.
2. Description of the Related Art
The density of electronic components mounted on chip carriers, such as printed circuit boards, is steadily increasing. This is a continuous process because such components are steadily being more compactly made, and because the number of leads, pins and/or solder ball arrays required on the corresponding chip carrier substrates is increasing in accordance with the reductions in the sizes of electronic apparatuses and improvements in their performances. Further, in response to demands for electronic apparatuses having higher speeds, it has become necessary to shorten circuit distances and thus reduce the time required for transferring electric signals. As a consequence of all this, the importance of chip carriers having a plurality of circuit layers, i.e., multilayer chip carriers, is constantly increasing.
To build a multilayer chip carrier, electrical connections must be formed between different circuit layers. For example, conventional multilayer chip carriers include through holes that penetrate the entire chip carrier substrate, the internal surfaces of which through holes are copper plated to provide electrical connections between different circuit layers. However, because through holes are formed using a mechanical method, such as one that involves the use of a mechanical drill, the substrate surface area consumed by the through holes is large, which is inconsistent with the need to increase electronic component density. If, for example, 10.sup.4 or more through holes are to be formed in a multi-layer chip carrier substrate, the manufacturing costs will be high and the process will not be practical.
An alternative to the use of copper plated through holes for electrically connecting circuit layers in multi-layer chip carriers is the use of photolithographically formed via holes, called photo-vias, for making such connections. (See, for example, Japanese Unexamined Patent Publication No. Hei 4-148590). Here, a photosensitive resin dielectric layer is formed on a first circuit layer, which has been formed on a substrate. This is achieved, for example, by depositing a liquid photosensitive resin dielectric material onto the first circuit layer using a curtain coater or a roll coater, and then drying the deposited material. Alternatively, a dry film of photosensitive resin dielectric material is pressure bonded to is the first circuit layer. Then, the photosensitive dielectric layer is photolithographically processed, i.e., exposed and developed, to form a predetermined pattern of photo-vias that penetrate only the dielectric layer. A second circuit layer is formed on the surface of the dielectric layer and the internal surfaces of the photo-vias are metallized. As a result, electrical connections are formed between the first and second circuit layers.
In this specification, a method for forming a chip carrier that includes at least two circuit layers and an intervening dielectric layer and that uses the above process is called a build-up method. A multilayer chip carrier, when fabricated by the assignee of the present application using the build-up method, is called a Surface Laminar Circuit (TM) (SLC) chip carrier. Significantly, in the case of an SLC chip carrier, the photo-vias used to make electrical connections between two circuit layers can be simultaneously and collectively formed by exposure and development, and the manufacturing costs remain stable, regardless of the number of photo-vias. Moreover, it is possible to form photo-vias having diameters which are much smaller than the diameters of via holes formed by drilling, and having a precise pattern. Consequently, the build-up method is regarded as the most effective method for implementing an increase in the component density of chip carriers.
Well known dielectric layers employed in the build-up method include denatured epoxy resin, which does not contain a photopolymerization initiator; a photosensitive dry film; a photosensitive resin coated on a non-photosensitive resin, such as a thin polyimide film; and a photosensitive resin employed by itself. Several recent unexamined Japanese patent publications feature the build-up method. For example, a multilayer chip carrier substrate employing a dielectric layer consisting of a photosensitive resin is disclosed in Japanese Unexamined Patent Publication No. Hei 8-18242. In this publication, a photosensitive resin consisting of an acrylic resin, a photopolymerized monomer, a photopolymerization initiator, a filler and a solvent is disclosed that can improve the features of the photosensitive resin, such as its heat resistance, chemical resistance, dielectric strength, permittivity and resolution. In addition, a method for forming a single dielectric layer by the lamination of two photosensitive dry film layers is disclosed in Japanese Unexamined Patent Publication No. Hei 8-152711. In this publication, in order to achieve high chemical resistance and high adhesion to copper plating, a first photosensitive dry film resin layer is provided which intimately contacts the copper plating layer. High chemical resistance and high dielectric strength are achieved by using a second photosensitive dry film resin layer that is formed under the first photosensitive dry film resin layer.
The present invention involves a problem associated with the use of what are initially liquid photosensitive dielectric layers, not dry film photosensitive layers. This problem is that of unwanted and unexpected extra via holes in the photosensitive dielectric layer, due to a phenomenon here termed "bubble eating", discussed below, and to the attachment of dust. It must be emphasized that "bubble eating" is a problem inherent to the formation of a chip carrier formed using a liquid resist coating, but does not occur when a chip carrier is formed using a photosensitive dry film, as in Japanese Unexamined Patent Publication No. Hei 8-152711.
In the build-up method, where a photosensitive dielectric layer is formed by applying a liquid resist coating, one generally employs a denatured epoxy resin that does not contain a photopolymerization initiator. The denatured epoxy resin has an epoxy group at either end of its molecular structure and a double bond in the center of its molecular structure. Consequently, when ultraviolet radiation is impinged upon the coated film, cross-linking only occurs in the upper portion of the coated film, and therefore only a relatively thin and weak photo-crosslinked layer is formed. In addition, the liquid resist coating is subject to "bubble eating," i.e., a foam is formed on the surface of the liquid resist consisting of tiny air bubbles produced during the coating procedure, and small holes are formed in the surface of the resist. Significantly, unwanted and unexpected extra via holes are formed in the dielectric layer due to "bubble eating", irregular coating and the attachment of dust particles during the liquid resist coating procedure. That is, when bubble eating occurs, light forms photo-crosslinks on the upper surface of the dielectric layer. However, because photo-crosslinks are not formed on the internal surfaces of the small holes produced by "bubble eating", a developing liquid can enter therein and cause voids. Also, because light can not reach the portions of the resist coating beneath the dust particles that become attached to the resist coating, these portions are not exposed and photo-crosslinks are not formed. For the above reasons, during the development procedure, unexpected voids occur at the "bubble eating" portions of the resist coating or at the dust attached portions, and thus, unwanted, extra via holes are formed.
Because the porosity of the photo-crosslinked layer formed with a low photosensitive dielectric layer is high, a developing liquid readily permeates the dielectric layer during the development process and produces unwanted, extra vias. Further, because the photo-crosslinked layer is not very hard, extra vias are caused by mechanical damage after the layer is exposed. Various other failures can also occur.
Conventionally, to overcome the problem of unwanted, extra vias, methods are employed for exposing the same pattern twice. This serves to reduce extra vias due to dust attachment and reinforces the photo-crosslinked layer by increasing the amount of light used for an exposure, thereby preventing the production of unwanted, extra vias caused by permeation with a developing liquid and by mechanical damage. However, using double exposures drastically deteriorates productivity. Furthermore, when increasing the amount of light used for exposure, "wrinkling" occurs on the surface of the dielectric layer due to a difference in the expansion/shrinkage rates for the photo-crosslinked layer (upper portion) and the non-photo-crosslinked layer (lower portion), and this prevents subsequent circuit formation.
To prevent such wrinkling, consideration has been given to the formation of a dielectric layer using a dry film method, which is disclosed in Japanese Unexamined Patent Publication No. Hei 8-152711 referred to above. With this dry film method, however, other problems arise, such as the irregular attachment of dry film when laminated, and the need for cleaning.